Akrida vs plain Claude

We hid 20 bugs in two open-source chip designs and asked both to find them, using the same AI model.

Akrida20 of 20

Plain Claude17 of 20

What counts as a catch

The tests pass on the original design and fail on the copy with the bug. Tests that fail on both are false alarms and don't count.

The 3 bugs only Akrida caught

ARREADY is not held low during reset
AXI4-Lite RAM·hard
cmd_ready stays high one cycle after a stop command, so a back-to-back command is accepted and dropped
I2C master·mediumReal bug from the project's history
write_multiple after a read is not a direction change, so the master ACKs and keeps reading
I2C master·hardReal bug from the project's history

Every bug, design by design

I2C master

Akrida 10 of 10 · Plain Claude 8 of 10

Show all 10 bugs

Hidden bugPlain ClaudeAkrida

B01
R/W bit in the address byte is inverted
B01easy
Plain Claude:Caught
Akrida:Caught
B02
Address bits are sent LSB first
B02easy
Plain Claude:Caught
Akrida:Caught
B03
m_axis_data_tlast is never set on the read that ends with STOP
B03easy
Plain Claude:Caught
Akrida:Caught
B04
A missing ACK on the address byte is not reported on missed_ack
B04medium
Plain Claude:Caught
Akrida:Caught
B05
The last byte read before STOP is ACKed instead of NACKed
B05medium
Plain Claude:Caught
Akrida:Caught
B06
Bytes in the middle of a multi-byte read are NACKed, so the slave stops sending
B06medium
Plain Claude:Caught
Akrida:Caught
B07
cmd_ready stays high one cycle after a stop command, so a back-to-back command is accepted and dropped
B07mediumReal bug from the project's history
Plain Claude:Missed
Akrida:Caught
B08
Clock stretching is ignored on written bits: the master times the SCL high phase from when it releases SCL
B08hard
Plain Claude:Caught
Akrida:Caught
B09
A write to a different address while the bus is held continues the old transfer instead of issuing a repeated START
B09hard
Plain Claude:Caught
Akrida:Caught
B10
write_multiple after a read is not a direction change, so the master ACKs and keeps reading
B10hardReal bug from the project's history
Plain Claude:Missed
Akrida:Caught

AXI4-Lite RAM

Akrida 10 of 10 · Plain Claude 9 of 10

Show all 10 bugs

Hidden bugPlain ClaudeAkrida

B01
Every write returns SLVERR instead of OKAY
B01easy
Plain Claude:Caught
Akrida:Caught
B02
WSTRB is ignored; all four byte lanes are always written
B02easy
Plain Claude:Caught
Akrida:Caught
B03
Reads return the word one above the addressed word
B03easy
Plain Claude:Caught
Akrida:Caught
B04
Byte lane 0 is never written
B04easy
Plain Claude:Caught
Akrida:Caught
B05
Byte lane 3 is gated by WSTRB[2] instead of WSTRB[3]
B05medium
Plain Claude:Caught
Akrida:Caught
B06
RRESP is SLVERR whenever the returned word has its top bit set
B06medium
Plain Claude:Caught
Akrida:Caught
B07
RVALID is a one-cycle pulse and drops even when RREADY is low
B07medium
Plain Claude:Caught
Akrida:Caught
B08
A write is accepted as soon as AWVALID is high, without waiting for WVALID
B08medium
Plain Claude:Caught
Akrida:Caught
B09
Write address drops its top bit, so writes above 0x8000 alias onto the lower half
B09hard
Plain Claude:Caught
Akrida:Caught
B10
ARREADY is not held low during reset
B10hard
Plain Claude:Missed
Akrida:Caught

How we ran it

Same model on both sides: Claude Opus 5.5, same effort, same spec and port list.
Neither one saw the design's code.
Plain Claude gets one prompt and up to 3 retries on compile errors, with no simulation feedback.
Akrida runs its full loop: plan, write, simulate, sort failures, fix, add tests.
One trial per design so far. Two simpler designs (a FIFO and a UART) are left out: plain Claude already caught all 10 bugs in each.

Cost and time

Design	Akrida	Plain Claude
AXI4-Lite RAM	$2.34 · 20 min	$1.31 · 12 min
I2C master	Not measured (part of the run reused earlier results)	$2.47 · 20 min

AXI4-Lite RAM
Akrida $2.34 · 20 min
Plain Claude $1.31 · 12 min
I2C master
Akrida Not measured (part of the run reused earlier results)
Plain Claude $2.47 · 20 min

The 3 bugs only Akrida caught

ARREADY is not held low during reset

AXI4-Lite RAM·hard

cmd_ready stays high one cycle after a stop command, so a back-to-back command is accepted and dropped

I2C master·mediumReal bug from the project's history

write_multiple after a read is not a direction change, so the master ACKs and keeps reading

I2C master·hardReal bug from the project's history

Every bug, design by design

I2C master

Akrida 10 of 10 · Plain Claude 8 of 10

Show all 10 bugs

Hidden bugPlain ClaudeAkrida

B01
R/W bit in the address byte is inverted
B01easy
Plain Claude:Caught
Akrida:Caught
B02
Address bits are sent LSB first
B02easy
Plain Claude:Caught
Akrida:Caught
B03
m_axis_data_tlast is never set on the read that ends with STOP
B03easy
Plain Claude:Caught
Akrida:Caught
B04
A missing ACK on the address byte is not reported on missed_ack
B04medium
Plain Claude:Caught
Akrida:Caught
B05
The last byte read before STOP is ACKed instead of NACKed
B05medium
Plain Claude:Caught
Akrida:Caught
B06
Bytes in the middle of a multi-byte read are NACKed, so the slave stops sending
B06medium
Plain Claude:Caught
Akrida:Caught
B07
cmd_ready stays high one cycle after a stop command, so a back-to-back command is accepted and dropped
B07mediumReal bug from the project's history
Plain Claude:Missed
Akrida:Caught
B08
Clock stretching is ignored on written bits: the master times the SCL high phase from when it releases SCL
B08hard
Plain Claude:Caught
Akrida:Caught
B09
A write to a different address while the bus is held continues the old transfer instead of issuing a repeated START
B09hard
Plain Claude:Caught
Akrida:Caught
B10
write_multiple after a read is not a direction change, so the master ACKs and keeps reading
B10hardReal bug from the project's history
Plain Claude:Missed
Akrida:Caught

AXI4-Lite RAM

Akrida 10 of 10 · Plain Claude 9 of 10

Show all 10 bugs

Hidden bugPlain ClaudeAkrida

B01
Every write returns SLVERR instead of OKAY
B01easy
Plain Claude:Caught
Akrida:Caught
B02
WSTRB is ignored; all four byte lanes are always written
B02easy
Plain Claude:Caught
Akrida:Caught
B03
Reads return the word one above the addressed word
B03easy
Plain Claude:Caught
Akrida:Caught
B04
Byte lane 0 is never written
B04easy
Plain Claude:Caught
Akrida:Caught
B05
Byte lane 3 is gated by WSTRB[2] instead of WSTRB[3]
B05medium
Plain Claude:Caught
Akrida:Caught
B06
RRESP is SLVERR whenever the returned word has its top bit set
B06medium
Plain Claude:Caught
Akrida:Caught
B07
RVALID is a one-cycle pulse and drops even when RREADY is low
B07medium
Plain Claude:Caught
Akrida:Caught
B08
A write is accepted as soon as AWVALID is high, without waiting for WVALID
B08medium
Plain Claude:Caught
Akrida:Caught
B09
Write address drops its top bit, so writes above 0x8000 alias onto the lower half
B09hard
Plain Claude:Caught
Akrida:Caught
B10
ARREADY is not held low during reset
B10hard
Plain Claude:Missed
Akrida:Caught

How we ran it

Same model on both sides: Claude Opus 5.5, same effort, same spec and port list.

Neither one saw the design's code.

Plain Claude gets one prompt and up to 3 retries on compile errors, with no simulation feedback.

Akrida runs its full loop: plan, write, simulate, sort failures, fix, add tests.

One trial per design so far. Two simpler designs (a FIFO and a UART) are left out: plain Claude already caught all 10 bugs in each.

Cost and time

Design	Akrida	Plain Claude
AXI4-Lite RAM	$2.34 · 20 min	$1.31 · 12 min
I2C master	Not measured (part of the run reused earlier results)	$2.47 · 20 min

AXI4-Lite RAM
Akrida $2.34 · 20 min
Plain Claude $1.31 · 12 min
I2C master
Akrida Not measured (part of the run reused earlier results)
Plain Claude $2.47 · 20 min