Some blocks show sample data (marked sample). Real pipeline and benchmark runs replace it block by block as they land in build/.

Verification overview

Every block's spec, tests, runs and bugs in one place. Designers see results here without asking DV.

Blocks
5
10 runs recorded
Requirements verified
42/77
checked, covered and passing
Open design bugs
1
3 fixed and verified by a rerun
Hidden bugs caught
26/30
vanilla Claude: 7/30

Blocks

Latest run per block

BlockLast commit verifiedStatusRequirementsCoverage pointsLine covOpen bugs
axil_ramc0e55b1 · Hold RVALID until RREADY; clear ARREADY in resetpassing
18/18
27/2798.9%0sample
i2c_master–no runs
0/14
––0
sync_fifo26b3a7b · Merge pull request #13 from kavin1001/claude/project-thread-9kzddmpassing
17/17
43/4382.1%0
uart–no runs
0/20
––0
uart_tx77b1d20 · UART TX with parity1 req failing
7/8
13/1396.1%1sample

Akrida vs vanilla Claude

Hidden injected bugs caught, latest benchmark per design

Details
sync_fifosample
Akrida
9/10Vanilla
0/10

Vanilla testbench fails on the clean design, so none of its failures count.

uart_txsample
Akrida
8/10Vanilla
4/10
axil_ramsample
Akrida
9/10Vanilla
3/10

Akrida spent $15.80 and 59m 58s in total; vanilla $1.65 and 9m 15s.

Recent runs

All runs
WhenBlockCommitStatusIterationsBugs filedWall clock
Oct 28, 16:02 UTCuart_tx77b1d20 · UART TX with parity1 req failing3117m 3s
Oct 28, 09:10 UTCaxil_ramc0e55b1 · Hold RVALID until RREADY; clear ARREADY in resetpassing103m 18s
Oct 27, 14:22 UTCaxil_rama71d0e4 · Gate byte lanes with WSTRB2 req failing124m 2s
Oct 26, 10:15 UTCaxil_ram3f9c2ab · Add AXI-Lite RAM controller3 req failing4323m 4s
Oct 25, 07:09 UTCsync_fifolocal runrunning00–
Oct 25, 06:39 UTCsync_fifo26b3a7b · Merge pull request #13 from kavin1001/claude/project-thread-9kzddmpassing107m 52s
Oct 25, 06:22 UTCsync_fifolocal runrunning00–
Oct 25, 06:10 UTCsync_fiforeplay of 20261029-1105171 req failing2110m 11s