Run on Oct 25, 06:39 UTC

Verification plan for sfifo in the target configuration (BW=8, LGFLEN=4 so depth 16, OPT_ASYNC_READ=0, OPT_WRITE_ON_FULL=0, OPT_READ_ON_EMPTY=0). The DUT has a plain valid/ready-less FIFO interface with no AXI4-Lite port, so no library agent is used. A custom active driver applies i_reset, i_wr, i_data and i_rd, changing them only away from the rising edge. A passive monitor samples all inputs and outputs at every rising edge. A cycle-accurate reference model is the main checker. It holds a queue of up to 16 entries and decides acceptance from the DUT-visible state before the edge: write accepted = i_wr && !full && !reset, read accepted = i_rd && !empty && !reset. It updates the queue at each edge and predicts o_fill, o_empty, o_full and o_data (the queue head) for the following cycle. The scoreboard compares every cycle: the status outputs always, and o_data whenever o_empty is low. Coverage collects fill level, operation mix, boundary transitions, data bit toggles, pointer wrap and reset context. The main risks are the registered read path breaking first-word fall-through and the boundaries 0/1/15/16 with simultaneous read and write.

All tests begin with a multi-cycle reset that has random i_wr, i_rd and i_data asserted during it. Then run the following tests: 1. Smoke: write one word, see it fall through, read it. 2. Fill and drain: 16 writes from empty, a 17th write attempt while full (with and without i_rd), then 16 reads plus an extra read attempt on empty. Run with data patterns 0x00, 0xFF, walking-1, walking-0, 0x55/0xAA and incrementing. 3. Boundary simultaneous read/write: hold the FIFO at fill 0, 1, 2, 8, 15 and 16, apply i_wr&&i_rd for one cycle and for long bursts, and check each. 4. Read latency: write a word into an empty FIFO and then read it in the very next cycle. Do back-to-back reads that drain to empty. Do back-to-back writes into empty while reading every cycle. 5. Wrap: stream more than 100 words with a steady-state fill of 1, 8 and 15, so the internal pointers wrap many times. 6. Reset: assert reset at fill 0, 1, 8, 15 and 16. Assert it with i_wr/i_rd high, for 1 cycle and for many cycles, and in the middle of a simultaneous read/write. After each reset, check that no stale data appears. Write in the first cycle after reset release. 7. Constrained-random: many seeds with i_wr/i_rd probabilities swept across producer-heavy (90/10), consumer-heavy (10/90), balanced (50/50) and full-rate (100/100) mixes. Use random i_data and sparse random resets. The reference model checks every cycle in all tests. Continue until all coverage points are hit.