Run on Oct 25, 06:22 UTC

Verification plan for sfifo (BW=8, LGFLEN=4, OPT_ASYNC_READ=0, OPT_WRITE_ON_FULL=0, OPT_READ_ON_EMPTY=0): a single-clock, 16-deep, 8-bit first-word fall-through FIFO with a registered read path. The DUT has plain valid-style ports and no bus protocol, so the AXI4-Lite library does not apply. The testbench uses three pieces: a custom FIFO-port driver, a passive monitor that samples all ports at every rising edge, and a cycle-accurate reference model. The model is a SystemVerilog queue of up to 16 bytes plus a fill counter. On every edge it decides acceptance from its own state: a write is accepted when i_wr is high and the model is not full; a read is accepted when i_rd is high and the model is not empty; on reset the model is cleared. A scoreboard compares the DUT against the model every cycle: o_fill, o_empty and o_full always, and o_data whenever the model is non-empty. A popped-word checker also logs each accepted read for ordering and loss/duplication analysis. The main risks are: the registered read path showing stale data after a write into an empty FIFO or after a simultaneous read/write at fill 1 or 2, pointer wrap-around, full/empty boundary handling of simultaneous requests, and reset while requests are active.

All stimulus is driven shortly after the rising edge (or on the falling edge) so setup timing is clean. Every check samples DUT outputs just before the next rising edge, against model state updated at the previous edge. Tests run in this order: 1) Reset/smoke: hold i_reset for several cycles with i_wr, i_rd and i_data toggling randomly. Then release and check the empty state. 2) Fill/drain directed: write 16 words with distinct values from empty, checking fill after each one. Attempt a 17th write and further writes with new data while full. Then read all 16 and check order. Attempt extra reads while empty. 3) Boundary simultaneous-access directed: at fill 0, 1, 2, 15 and 16, drive i_wr=1 and i_rd=1 for one cycle and for long streaks. Check fill, flags and o_data the next cycle. 4) Registered-read-path directed: write a single word into an empty FIFO and check o_data the very next cycle. Do write then immediate read on consecutive cycles. Do back-to-back read streaks to empty, and alternating single-word ping-pong. 5) Wrap-around: stream at least 100 words with a mix of throughputs, so the read and write pointers wrap many times at every fill level, including wrap while full and while at fill 1. 6) Data patterns: walking-1, walking-0, 0x00, 0xFF, 0xAA and 0x55, plus an incrementing counter so loss or duplication is easy to spot. 7) Reset injection: assert reset at fill 0, 1, 8, 15 and 16. Do this with i_wr and/or i_rd high in the reset cycle, during simultaneous traffic, and in the middle of a multi-cycle reset. After each reset, refill with a new data signature and check that no pre-reset word ever appears. 8) Constrained-random traffic: many seeds, each with several phases: - write-heavy (P(wr)=0.9, P(rd)=0.2) to sit at full; - read-heavy to sit at empty; - balanced 0.5/0.5; - always-both (1/1); - bursty idle gaps. Every phase uses random data and random sparse reset (about 1%). The scoreboard checks every cycle. 9) Long soak with the reference model and coverage closure on all listed coverage points.