UART transmitter

Sample

uart_tx·Serialises bytes from a valid/ready input stream onto a single TX line.

1 bug to fix

Last checked Oct 14 on commit 77b1d20, “UART TX with parity”.

7 of 8

requirements pass

13 of 13

scenarios tested

bug found, not fixed yet

Sample data. These runs are made up to show what Akrida produces. A real run replaces them.

1 still needs a fix.

To fixREQ-TX-5

Should happen

Two stop bits (high) before the next start bit or idle

What happened

Line low after one stop bit; next start bit begins one bit period early

Proof from the simulation log

UVM_ERROR @ 3302000 [REQ-TX-5] stop bit 2 sampled low, two_stop=1, prescale=16