uart_tx·Serialises bytes from a valid/ready input stream onto a single TX line.
UART transmitter. Valid/ready stream driver, line monitor that decodes frames, bit-timing checker.
Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.
TXD is high whenever no frame is being sent, including during reset.
REQ-TX-1How it's tested: Line monitor checks TXD every cycle outside frames
A frame starts with one start bit (low) lasting prescale cycles.
How it's tested: Bit-timing checker
The 8 data bits follow, least significant bit first, each lasting prescale cycles.
How it's tested: Serial-to-byte model compares each frame
When parity_en is 1, an even parity bit follows the data bits.
How it's tested: Parity computed in the model
The frame ends with one stop bit (high), or two when two_stop is 1.
How it's tested: Frame length checker
A byte is accepted only in a cycle where s_tvalid and s_tready are both high.
How it's tested: Stream monitor counts handshakes
s_tready is low while a frame is being sent.
How it's tested: Cycle check
prescale and parity_en are sampled when a byte is accepted; changes mid-frame do not affect the current frame.
How it's tested: Change prescale mid-frame; model uses sampled value