uart_tx·Serialises bytes from a valid/ready input stream onto a single TX line.
This is everything Akrida knew about the design. It never sees the design's code.
uart_tx serialises bytes from a valid/ready input stream onto a single
TX line: one start bit, 8 data bits LSB first, an optional parity bit and
one or two stop bits. The baud rate is set by a clock divider register.
| Port | Dir | Width | Description |
|---|---|---|---|
| clk | in | 1 | Clock |
| rst | in | 1 | Synchronous reset, active high |
| s_tdata | in | 8 | Byte to send |
| s_tvalid | in | 1 | Byte valid |
| s_tready | out | 1 | Ready for the next byte |
| prescale | in | 16 | Clock cycles per bit |
| parity_en | in | 1 | Add an even parity bit |
| two_stop | in | 1 | Send two stop bits |
| txd | out | 1 | Serial output, idle high |
| busy | out | 1 | High while a frame is being sent |
prescale cycles.prescale cycles.parity_en is 1, an even parity bit follows the data bits.two_stop is 1.s_tvalid and s_tready are both high.s_tready is low while a frame is being sent.prescale and parity_en are sampled when a byte is accepted; changes mid-frame do not affect the current frame.