uart_tx·Serialises bytes from a valid/ready input stream onto a single TX line.
The test code Akrida wrote for this design: SystemVerilog UVM, compiled with Verilator. It's yours to keep.
1// Generated by Akrida (sample data). The real file comes from the testbench writer agent.2`include "uvm_macros.svh"3import uvm_pkg::*;4import axil_pkg::*;5 6class uart_tx_model;7 bit [31:0] mem [int];8 function bit [31:0] read(int unsigned word);9 return mem.exists(word) ? mem[word] : 32'h0; // REQ-MEM-310 endfunction11 function void write(int unsigned word, bit [31:0] data, bit [3:0] strb);12 bit [31:0] old = read(word);13 for (int i = 0; i < 4; i++) // REQ-WR-214 if (strb[i]) old[8*i +: 8] = data[8*i +: 8];15 mem[word] = old;16 endfunction17endclass18 19class akrida_scoreboard extends uvm_scoreboard;20 `uvm_component_utils(akrida_scoreboard)21 uvm_analysis_imp #(axil_item, akrida_scoreboard) imp;22 uart_tx_model model = new();23 int unsigned cov [string];24 25 function new(string name, uvm_component parent);26 super.new(name, parent);27 imp = new("imp", this);28 endfunction29 30 function void write(axil_item t);31 if (t.is_write) begin32 if (t.resp != 2'b00)33 `uvm_error("REQ-WR-3", $sformatf("BRESP=%0b at addr 0x%04h, expected OKAY", t.resp, t.addr))34 model.write(t.addr >> 2, t.data, t.strb);35 end else begin36 bit [31:0] exp = model.read(t.addr >> 2);37 if (t.data !== exp)38 `uvm_error("REQ-RD-2", $sformatf("RDATA=0x%08h at addr 0x%04h, expected 0x%08h", t.data, t.addr, exp))39 end40 endfunction41 42 function void report_phase(uvm_phase phase);43 foreach (cov[id]) `uvm_info("AKRIDA_COV", $sformatf("%s %0d", id, cov[id]), UVM_NONE)44 endfunction45endclass46 47// ... env, sequences, test and tb_top follow in the generated file.