Checked commit 77b1d20, “UART TX with parity”.
3 rounds · fixed 2 mistakes in its own tests · 17 min · $4.17
UART transmitter. Valid/ready stream driver, line monitor that decodes frames, bit-timing checker.
Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.
The line monitor shifts bits in MSB first; the spec says LSB first and the DUT is consistent with that. Monitor fixed.
Error message shows observed equals expected; the comparison used !== on a 2-state copy. Checker fixed.
With two_stop=1 the line goes low one bit early; stimulus is a single byte with no other activity.
UVM_ERROR @ 3302000 [REQ-TX-5] second stop bit low at 3302000 with two_stop=1