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AXI4-Lite RAM

Sample

axil_ram·A single-port memory exposed as an AXI4-Lite slave.

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Overview Requirements18 Runs3 Testbench Spec

All 18 requirements pass

Last checked Oct 14 on commit c0e55b1, “Hold RVALID until RREADY; clear ARREADY in reset”.

18 of 18

requirements pass

27 of 27

scenarios tested

3

bugs found, all fixed

Sample data. These runs are made up to show what Akrida produces. A real run replaces them.

Bugs Akrida found

All 3 were fixed by the designer and passed when Akrida checked again.

WSTRB ignored: all four byte lanes written on partial writes
REQ-WR-2 · Found Oct 12 · fixed Oct 13
Fixed and re-checkedREQ-WR-2
WSTRB ignored: all four byte lanes written on partial writes
Should happen
Lanes with WSTRB[i]=0 keep their previous value
What happened
Write 0xAABBCCDD with WSTRB=4'b0001 to 0x0040 over 0x11223344 reads back 0xAABBCCDD
Proof from the simulation log
UVM_ERROR @ 182000 [REQ-WR-2] addr 0x0040 RDATA=0xaabbccdd expected 0x112233dd; 41 more with WSTRB != 4'b1111
RVALID drops after one cycle while RREADY is low
REQ-HS-1 · Found Oct 12 · fixed Oct 14
Fixed and re-checkedREQ-HS-1
RVALID drops after one cycle while RREADY is low
Should happen
RVALID stays high with stable RDATA until RREADY
What happened
RVALID high for one cycle at 233000, low at 243000 with RREADY held low
Proof from the simulation log
UVM_ERROR @ 243000 [REQ-HS-1] RVALID deasserted without handshake (rready=0, stall=7 cycles)
ARREADY high during reset
REQ-HS-6 · Found Oct 12 · fixed Oct 14
Fixed and re-checkedREQ-HS-6
ARREADY high during reset
Should happen
ARREADY low in every cycle while rst is high
What happened
ARREADY=1 at 30000 and 40000 with rst=1 after an ARVALID was driven during reset
Proof from the simulation log
UVM_ERROR @ 30000 [REQ-HS-6] s_axil_arready=1 while rst=1