Checked commit 3f9c2ab, “Add AXI-Lite RAM controller”.
4 rounds · fixed 1 mistake in its own tests · 23 min · $6.42
Single-port AXI4-Lite RAM. Reuse the axil agent; byte-lane reference model; protocol, reset and back-pressure checkers.
Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.
The monitor samples WREADY on the negedge but the handshake completes on the posedge; the spec allows BVALID in the same cycle as the handshake. The check is off by one cycle.
Model applies WSTRB=0001 per spec; DUT overwrote all lanes. Driver waveform shows WSTRB=0001 at the handshake, so stimulus is correct.
RREADY was held low by the driver's back-pressure knob; spec requires RVALID to stay high. No protocol error from the testbench precedes it.
New reset-phase sequence drives ARVALID during reset; spec says ARREADY must be low while rst is high.
UVM_ERROR @ 182000 [REQ-WR-2] addr 0x0040 RDATA=0xaabbccdd expected 0x112233dd
UVM_ERROR @ 243000 [REQ-HS-1] RVALID deasserted without handshake
UVM_ERROR @ 30000 [REQ-HS-6] s_axil_arready=1 while rst=1