Akrida
Check

Run on Oct 13, 14:22 UTC

Sample

Checked commit a71d0e4, “Gate byte lanes with WSTRB”.

Replay this run

1 bug fixed, 2 still to fix

1 round · 4 min · $0.88

  1. Read the spec
    Planned 18 requirements and 27 scenarios to test.
    Show the plan

    Single-port AXI4-Lite RAM. Reuse the axil agent; byte-lane reference model; protocol, reset and back-pressure checkers.

    Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.

  2. Wrote the tests
    First version: tb_v0.sv, a complete UVM testbench.
  3. Round 1: 2 failures
    • Both were bugs already reported.
    Every scenario reached.
    27 of 27 scenarios reached · code coverage 98.4% · simulated in 1 min 37 s
  4. Done: no new bugs. 2 reported earlier still fail.
Technical details
Agent steps
  1. 1Spec analyst wrote the verification plan
  2. 2Testbench writer wrote the UVM testbench
  3. 3Triage agent diagnosed failures
Final UVM_ERROR lines
UVM_ERROR @ 243000 [REQ-HS-1] RVALID deasserted without handshake
UVM_ERROR @ 30000 [REQ-HS-6] s_axil_arready=1 while rst=1
Model
claude-opus-5-5
Calls
3
Tokens in / out
110,000 / 22,000
Cost
$0.88
Coverage points hit
27 of 27