axil_ram·A single-port memory exposed as an AXI4-Lite slave.
Single-port AXI4-Lite RAM. Reuse the axil agent; byte-lane reference model; protocol, reset and back-pressure checkers.
Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.
Reuses the verified axil protocol library.
The memory holds 2^(ADDR_WIDTH - log2(STRB_WIDTH)) words of DATA_WIDTH bits (16,384 words of 32 bits with the defaults).
REQ-MEM-1How it's tested: Reference model sized from parameters; scoreboard checks every address it touches
Addresses are byte addresses. The word index is the address with the low log2(STRB_WIDTH) bits dropped. The low address bits do not affect which word is accessed.
REQ-MEM-2How it's tested: Scoreboard maps byte address to word index; reads at unaligned offsets compared to the model
Every word reads as zero before it is first written.
REQ-MEM-3How it's tested: Model initialised to zero; first read of an untouched word must be 0
Reset does not clear the memory contents.
REQ-MEM-4How it's tested: Write, pulse reset, read back and compare
Every address in the range is valid. Writes to one word never change any other word.
REQ-MEM-5How it's tested: Full scoreboard compare on random traffic across the whole range
A write is accepted only once both the write address and the write data are valid. The slave may wait for both before raising AWREADY and WREADY.
REQ-WR-1How it's tested: Protocol checker: no AWREADY/WREADY handshake before both VALIDs
For each byte lane i, the byte is written only when WSTRB[i] is 1. Lanes with WSTRB[i] = 0 keep their previous value.
REQ-WR-2How it's tested: Byte-lane reference model; read-back after every partial write
Each accepted write produces exactly one write response with BRESP = OKAY (2'b00).
REQ-WR-3How it's tested: Response counter per accepted write; BRESP compared to 2'b00
A read issued after a write response has been received returns the newly written data.
REQ-WR-4How it's tested: Back-to-back write then read on the same address
Each accepted read address produces exactly one read data beat with RRESP = OKAY (2'b00).
REQ-RD-1How it's tested: Beat counter per accepted read; RRESP compared to 2'b00
RDATA holds the full word at the addressed location.
REQ-RD-2How it's tested: Scoreboard compares RDATA to the model
Once BVALID or RVALID is raised it stays high, with stable BRESP, RDATA and RRESP, until the master raises the matching READY.
REQ-HS-1How it's tested: Monitor assertion on BVALID/RVALID stability
BVALID is never high in a cycle before the one in which both the write address and write data handshakes complete. It may be high in that same cycle.
REQ-HS-2How it's tested: Cycle check in the protocol monitor
RVALID is never high in a cycle before the one in which the read address handshake completes. It may be high in that same cycle.
REQ-HS-3How it's tested: Cycle check in the protocol monitor
The slave must accept new transactions when the master holds BREADY or RREADY low for a long time and then releases them: no deadlock under back-pressure.
REQ-HS-4How it's tested: Watchdog on outstanding transactions
Address and data may arrive in either order and in different cycles; the slave must handle any skew between AWVALID and WVALID.
REQ-HS-5How it's tested: Driver skew knob swept; scoreboard compare
While rst is high, AWREADY, WREADY, BVALID, ARREADY and RVALID are all low.
REQ-HS-6How it's tested: Reset-phase checker samples every output each cycle
AWPROT and ARPROT do not affect behavior.
REQ-IGN-1How it's tested: Same traffic with random PROT values; scoreboard compare