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AXI4-Lite RAM

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axil_ram·A single-port memory exposed as an AXI4-Lite slave.

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Overview Requirements18 Runs3 Testbench Spec

All passSample
Hold RVALID until RREADY; clear ARREADY in reset
c0e55b1 · Oct 14, 09:10 · 1 round · 3 min
1 bug fixed, 2 still to fixSample
Gate byte lanes with WSTRB
a71d0e4 · Oct 13, 14:22 · 1 round · 4 min
Found 3 bugsSample
Add AXI-Lite RAM controller
3f9c2ab · Oct 12, 10:15 · 4 rounds · 23 min