Runs
Every run across all designs, newest first.
- Checking now· Synchronous FIFOOct 25, 08:02
- All pass· Synchronous FIFOMerge pull request #1326b3a7b · Oct 25, 06:39 · 1 round · 8 min
- Found 1 bug· UART transmitterSampleUART TX with parity77b1d20 · Oct 14, 16:02 · 3 rounds · 17 min
- All pass· AXI4-Lite RAMSampleHold RVALID until RREADY; clear ARREADY in resetc0e55b1 · Oct 14, 09:10 · 1 round · 3 min
- 1 bug fixed, 2 still to fix· AXI4-Lite RAMSampleGate byte lanes with WSTRBa71d0e4 · Oct 13, 14:22 · 1 round · 4 min
- Found 3 bugs· AXI4-Lite RAMSampleAdd AXI-Lite RAM controller3f9c2ab · Oct 12, 10:15 · 4 rounds · 23 min