Run on Oct 25, 06:10 UTC

Sample

Checked commit e2a9f43, “Parameterised sync FIFO”.

1 requirement failing

2 rounds · 10 min · $2.36

Read the spec
Planned 8 requirements and 9 scenarios to test.
Show the plan
Synchronous FIFO. Queue reference model, occupancy checks every cycle.
Directed reset and corner-case sequences first, then constrained-random traffic with back-pressure and skew knobs swept, then targeted sequences for any coverage hole the previous pass reported.
Wrote the tests
First version: tb_v0.sv, a complete UVM testbench.
Round 1: 1 failure
- Design bugPush+pop at fullREQ-FIFO-4
  Why Akrida thinks so
  The DUT blocks the push when full even though a pop happens in the same cycle; the spec says both succeed.
1 scenario weren't reached yet, so Akrida added tests for them. 1 new bug reported.
8 of 9 scenarios reached · code coverage 94.0% · simulated in 1 min 42 s
Round 2: 1 failure
- 1 failure was a bug already reported.
Every scenario reached.
9 of 9 scenarios reached · code coverage 100.0% · simulated in 2 min 18 s
Done: 1 requirement failing
- Push dropped on simultaneous push and pop when full

Technical detailsagent steps, final log, model and cost

Agent steps

Final UVM_ERROR lines

UVM_ERROR @ 88000 [REQ-FIFO-4] count went 16 -> 15 on push+pop while full, expected 16