Run on Oct 25, 07:09 UTC

Cycle-accurate verification plan for sfifo with BW=8, LGFLEN=4, OPT_ASYNC_READ=0, OPT_WRITE_ON_FULL=0, OPT_READ_ON_EMPTY=0. The testbench must override OPT_ASYNC_READ to 0, because the RTL default is 1. The plan has these parts. A simple valid-less driver on i_wr/i_data/i_rd/i_reset. A passive monitor that samples all ports at every rising edge. A golden reference model: a queue of 8-bit words updated at each edge using the spec's accept rules (write accepted iff i_wr && !full_model && !reset; read accepted iff i_rd && !empty_model && !reset). A scoreboard that compares o_fill, o_empty, o_full every cycle and o_data every cycle in which o_empty is low. SVA assertions cover the status invariants, the reset response and X-freedom. No AXI4-Lite port exists, so no library agent is used.

All tests run with parameters BW=8, LGFLEN=4, OPT_ASYNC_READ=0, OPT_WRITE_ON_FULL=0, OPT_READ_ON_EMPTY=0. The reference model and scoreboard check every cycle in every test, and the SVA invariants are always on. Drive inputs a small delay after the rising edge (or on the negedge) so that sampling is unambiguous. Each test starts with i_reset high for several cycles while i_wr/i_rd toggle with random data, to prove that inputs during reset are ignored. Directed tests: (1) Reset-state check. (2) Fill/drain: 16 writes from empty with distinct values. Check o_full appears exactly after the 16th write. Then issue 4 more writes while full (with i_rd low), then drain all 16 and check order. Then issue 4 extra reads while empty, then write one word and check it. (3) Single-word latency: write one word into empty and check o_empty falls and o_data is valid the next cycle. Hold i_rd low for many cycles and check o_data is stable. Then read it and check o_empty rises. (4) Simultaneous read/write at each fill level: fill 0, 1, 2, 8, 15, 16, with sustained back-to-back R/W bursts at fill 1 and fill 15. (5) Full plus i_wr plus i_rd: check only the read is accepted, the written word never appears, and o_full stays high during that cycle. (6) Empty plus i_wr plus i_rd: check only the write is accepted. (7) Wraparound: more than 64 words streamed at varying occupancy so the pointers wrap at least 4 times, including wrap while full and while at fill 1. (8) Data patterns: 0x00, 0xFF, 0x55, 0xAA, walking-1 and walking-0 across all 8 bits, written while i_data also toggles with i_wr low (noise that must be ignored). (9) Reset in each state (empty, 1, mid, 15, full) and coincident with a write, a read and both. After each reset, write a fresh pattern and confirm no pre-reset word ever appears. Includes back-to-back multi-cycle reset and a reset asserted for exactly one cycle. Constrained-random tests: (10) i_wr/i_rd probabilities swept over profiles: writer-heavy (90/10), reader-heavy (10/90), balanced (50/50), bursty (long on/off runs), and both at 100%. Random data, occasional random resets (about 1/500 cycles), at least 20k cycles per seed, multiple seeds. Closure: run until all functional coverage points listed are hit, including the cross of fill level (0, 1, 2..14, 15, 16) with {i_wr, i_rd, i_reset} combinations.