Akrida
Designs
Bugs
1
Benchmark
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Synchronous FIFO
sync_fifo
A single-clock first-in, first-out buffer.
Replay available
UART transmitter
uart_tx
Serialises bytes from a valid/ready input stream onto a single TX line.
Replay available
AXI4-Lite RAM
axil_ram
A single-port memory exposed as an AXI4-Lite slave.
Replay available
I2C master
i2c_master
A single-master I2C controller.
UART
uart
A full-duplex universal asynchronous receiver/transmitter.
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