Synchronous FIFOsync_fifo
A single-clock first-in, first-out buffer.
Replay available
UART transmitteruart_tx
Serialises bytes from a valid/ready input stream onto a single TX line.
Replay available
AXI4-Lite RAMaxil_ram
A single-port memory exposed as an AXI4-Lite slave.
Replay available
I2C masteri2c_master
A single-master I2C controller.
UARTuart
A full-duplex universal asynchronous receiver/transmitter.