I2C master

A read or write command has exactly one of read or (write / write_multiple) set. A command with only stop set is a stop command. Any other combination is ignored.

Write data for a write command is one byte from the write data stream. For write-multiple, bytes are taken until one with tlast.

Each read command produces exactly one byte on the read data stream. m_axis_data_tlast is 1 when the command also had stop set.

When the bus is idle, a read or write command begins with a START condition followed by the address byte (7-bit address, then R/W bit: 1 = read, 0 = write).

When the bus is held after a previous command, the master issues a repeated START and a new address byte if start is set, the address differs from the previous command's, or the direction changes. Otherwise the transfer continues with no new address phase.

A command with stop set ends with a STOP condition after its data. A stop command issues a STOP if the master holds the bus and is ignored otherwise.

Data and address bits are sent most significant bit first. SDA changes only while SCL is low, except to form START (SDA falls while SCL is high) and STOP (SDA rises while SCL is high).

After each address byte and each written data byte the master releases SDA for one SCL pulse and samples the slave's acknowledge. A high SDA is a missed acknowledge: missed_ack pulses for one cycle. The master continues the command regardless.

After each byte it reads, the master drives the acknowledge bit: ACK (SDA low) when the next command continues reading from the same slave without a new START, NACK (SDA high) otherwise, including before a STOP or repeated START.

Each SCL pulse the master generates is high for at least 2 × prescale clock cycles, measured from when SCL is actually high on the bus.

A slave may hold SCL low (clock stretching) for any time. The master never drives SCL low until it has seen SCL high and then waited the high time in REQ-TIM-1. Clock stretching never corrupts or shortens a bit.

For START and STOP, SDA changes at least prescale cycles after SCL is high, and SCL stays high at least prescale cycles after a START's SDA fall.

bus_control is high from this master's START until its STOP. bus_active is high between any START and the next STOP on the bus.

While rst is high, scl_o and sda_o are 1 (bus released), s_axis_cmd_ready, s_axis_data_tready, m_axis_data_tvalid, busy, bus_control, bus_active and missed_ack are 0.