UART

A frame is one start bit (0), DATA_WIDTH data bits sent least significant bit first, and one stop bit (1). There is no parity bit. The line idles at 1.

One bit time is 8 × prescale clock cycles. prescale is at least 1 and changes only while both the transmitter and receiver are idle.

A byte moves on the input stream in a cycle where s_axis_tvalid and s_axis_tready are both high, and on the output stream in a cycle where m_axis_tvalid and m_axis_tready are both high. Once raised, m_axis_tvalid and m_axis_tdata stay unchanged until the byte is taken, except as described in REQ-RX-6.

The upstream master holds s_axis_tdata stable and keeps s_axis_tvalid high until its byte is accepted.

Every byte accepted on the input stream is sent on txd as exactly one frame, in the order accepted. No accepted byte is dropped or sent twice.

The start bit and each data bit on txd last exactly one bit time. The stop bit lasts at least one bit time.

The transmitter sends one frame at a time. It never accepts a byte while a frame is in progress, and the next frame's start bit begins only after the previous stop bit has lasted a full bit time.

The start bit of a frame begins within one clock cycle of the handshake that accepted its byte.

tx_busy is high from the start bit through the stop bit of every frame and low while the transmitter is idle.

txd is 1 while idle and while rst is high.

A high-to-low transition on rxd while the receiver is idle marks a possible start bit. The receiver samples the line in the middle of the start bit and of each following bit.

If rxd is high again when the middle of the start bit is sampled, the start is false: the receiver returns to idle and produces no byte and no error. Low pulses shorter than half a bit time are therefore ignored.

The data bits of a frame are assembled least significant bit first. When the stop bit is sampled as 1, the byte is presented on m_axis_tdata with m_axis_tvalid high.

The receiver decodes frames correctly when the sender's bit time differs from the nominal 8 × prescale cycles by up to ±3%.

When the stop bit is sampled as 0, rx_frame_error is high for exactly one clock cycle and no byte is presented. A byte already waiting on the output stream is not affected.

When a frame completes while the previous byte is still waiting (m_axis_tvalid high and not yet taken), the new byte replaces the waiting one on m_axis_tdata, m_axis_tvalid stays high, and rx_overrun_error is high for exactly one clock cycle. The replaced byte is lost.

Outside the cases in REQ-RX-5 and REQ-RX-6, rx_frame_error and rx_overrun_error stay low.

rx_busy is high while a frame is being received.

While rst is high, s_axis_tready, m_axis_tvalid, tx_busy, rx_busy, rx_overrun_error and rx_frame_error are low and txd is high.

The transmitter and receiver operate at the same time without affecting each other (full duplex).