UART: block specification

1. Overview

uart is a full-duplex universal asynchronous receiver/transmitter. Bytes written on a valid/ready stream input are sent as serial frames on txd; serial frames arriving on rxd are turned back into bytes on a valid/ready stream output. The transmitter and receiver run independently and share only the clock, reset and baud-rate setting.

                  +---------------------------------+
  s_axis_tdata -->|                                 |
  s_axis_tvalid ->|  transmitter  --- shift out --> |--> txd
  s_axis_tready <-|                                 |--> tx_busy
                  |                                 |
  m_axis_tdata <--|                                 |
  m_axis_tvalid <-|  receiver    <--- sample ---    |<-- rxd
  m_axis_tready ->|                                 |--> rx_busy
                  |                                 |--> rx_overrun_error
                  |                                 |--> rx_frame_error
  prescale ------>|  bit time = 8 * prescale clocks |
                  +---------------------------------+

2. Parameters

The verification target uses the default, 8 data bits.

3. Ports

4. Functional requirements

Frame format and timing

• REQ-FMT-1 A frame is one start bit (0), DATA_WIDTH data bits sent least significant bit first, and one stop bit (1). There is no parity bit. The line idles at 1.
• REQ-FMT-2 One bit time is 8 × prescale clock cycles. prescale is at least 1 and changes only while both the transmitter and receiver are idle.

Stream handshakes

• REQ-HS-1 A byte moves on the input stream in a cycle where s_axis_tvalid and s_axis_tready are both high, and on the output stream in a cycle where m_axis_tvalid and m_axis_tready are both high. Once raised, m_axis_tvalid and m_axis_tdata stay unchanged until the byte is taken, except as described in REQ-RX-6.
• REQ-HS-2 The upstream master holds s_axis_tdata stable and keeps s_axis_tvalid high until its byte is accepted.

Transmitter

• REQ-TX-1 Every byte accepted on the input stream is sent on txd as exactly one frame, in the order accepted. No accepted byte is dropped or sent twice.
• REQ-TX-2 The start bit and each data bit on txd last exactly one bit time. The stop bit lasts at least one bit time.
• REQ-TX-3 The transmitter sends one frame at a time. It never accepts a byte while a frame is in progress, and the next frame's start bit begins only after the previous stop bit has lasted a full bit time.
• REQ-TX-4 The start bit of a frame begins within one clock cycle of the handshake that accepted its byte.
• REQ-TX-5 tx_busy is high from the start bit through the stop bit of every frame and low while the transmitter is idle.
• REQ-TX-6 txd is 1 while idle and while rst is high.

Receiver

• REQ-RX-1 A high-to-low transition on rxd while the receiver is idle marks a possible start bit. The receiver samples the line in the middle of the start bit and of each following bit.
• REQ-RX-2 If rxd is high again when the middle of the start bit is sampled, the start is false: the receiver returns to idle and produces no byte and no error. Low pulses shorter than half a bit time are therefore ignored.
• REQ-RX-3 The data bits of a frame are assembled least significant bit first. When the stop bit is sampled as 1, the byte is presented on m_axis_tdata with m_axis_tvalid high.
• REQ-RX-4 The receiver decodes frames correctly when the sender's bit time differs from the nominal 8 × prescale cycles by up to ±3%.
• REQ-RX-5 When the stop bit is sampled as 0, rx_frame_error is high for exactly one clock cycle and no byte is presented. A byte already waiting on the output stream is not affected.
• REQ-RX-6 When a frame completes while the previous byte is still waiting (m_axis_tvalid high and not yet taken), the new byte replaces the waiting one on m_axis_tdata, m_axis_tvalid stays high, and rx_overrun_error is high for exactly one clock cycle. The replaced byte is lost.
• REQ-RX-7 Outside the cases in REQ-RX-5 and REQ-RX-6, rx_frame_error and rx_overrun_error stay low.
• REQ-RX-8 rx_busy is high while a frame is being received.

Reset and independence

• REQ-RST-1 While rst is high, s_axis_tready, m_axis_tvalid, tx_busy, rx_busy, rx_overrun_error and rx_frame_error are low and txd is high.
• REQ-DUP-1 The transmitter and receiver operate at the same time without affecting each other (full duplex).

5. Out of scope

Parity, more than one stop bit, flow control (RTS/CTS), break detection and receive FIFOs are not supported. Metastability on rxd is handled by the receiver's input register and is not checked in simulation.